1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an alternative magnetic tunneling junction configuration and a method for making such a structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
At various stages in the fabrication of semiconductor devices, it may be necessary to pattern one or more layers to form a semiconductor feature. Such a semiconductor feature may include, for example, a gate structure, an interconnect line, or a magnetic tunneling junction (MTJ) stack. The process parameters used for such a patterning process may affect the operation of the device comprising the semiconductor feature. For example, plasma etch techniques, which are typically used for metal etch processes, generally require temperatures greater than approximately 200° C. However, large temperature variations during a fabrication process of a semiconductor device may cause stress within the structures of the device. Consequently, temperature variations resulting from metal etch processes may degrade the performance and functionality of devices in some embodiments. In addition, high temperature etch processes may generally not be used with photolithographic resist masks since resist materials tend to degrade at temperatures greater than approximately 200° C. As such, a hardmask may be necessary during high temperature etch processes. In general, a hardmask layer may be formed by patterning the hardmask material using a resist mask and subsequently removing the resist mask. As such, using a hardmask may undesirably require more processing steps, increasing and complicating the fabrication process of the device.
In some embodiments, the use of a resist mask or a hardmask may additionally or alternatively depend on the etch chemistry used during the etch process of the semiconductor feature. For example, the use of a hardmask may be particularly advantageous in embodiments in which an etch chemistry that is not selective to the one or more layers of the semiconductor topography is used. For instance, an etch chemistry including an oxygen plasma is generally not more selective to layers of a semiconductor topography than to a resist mask. As such, an etch chemistry including an oxygen plasma may etch the resist mask at a similar or faster rate than adjacent layers. Consequently, a resist material may not adequately serve as a mask to pattern the semiconductor feature and thus, the use of a hardmask in such an embodiment may be needed. However, as stated above, the use of a hardmask undesirably requires additional fabrication time, increasing and complicating the fabrication process of the device.
Regardless of whether a resist mask or a hardmask is used to pattern a semiconductor feature, some etch processes used during the patterning process may alter or degrade the properties of layers or structures within the device. For example, an etch process including an oxygen plasma may degrade the magnetic properties of magnetic materials. As such, using an etch process including an oxygen plasma to pattern magnetic layers of a memory device including a MTJ, for example, may undesirably degrade the performance and/or functionality of the device. Moreover, some etch processes may cause material to be redeposited upon sidewalls of the semiconductor feature, varying the dimension of the semiconductor feature from its critical dimension specification. In some cases, such a redeposition of material may alter the functionality of the device or render the device inoperable. In addition or alternatively, sidewalls of semiconductor features may be exposed during some etch processes. In some cases, exposure of metal semiconductor feature surfaces, in particular, may allow shorts to occur across a metal feature, thereby degrading the functionality of the device. For example, a tunneling layer of a MJT may be susceptible to shorts occurring across the layer.
Therefore, it would be desirable to develop a method for etching metal layers within a semiconductor topography which overcomes one or more of the issues mentioned above. In particular, it would be advantageous to develop an etch process which allows the use of a resist mask and/or relatively low process temperatures. In addition, it may be desirable to develop an etch process which does not affect the properties of layers within a semiconductor topography, such that a device fabricated therefrom is not degraded or rendered inoperable. Moreover, it may be advantageous to fabricate a semiconductor device from such an etch process that is not susceptible to shorts occurring across its metal features.